1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a data input circuit of a semiconductor memory apparatus.
2. Related Art
In general, in order to perform a data input operation, a semiconductor memory apparatus commonly includes a plurality of data pads and a plurality of data input buffers connected to respective ones of the plurality of data pads. Accordingly, respective ones of the plurality of data input buffers perform a buffering operation on data synchronously with an internal clock transmitted from a Delay Locked Loop (DLL) circuit or a Phase Locked Loop (PLL) circuit. In order that respective data input buffers operate normally, a timing between the internal clock signals and respective input data signals, which is transmitted to respective data input buffers, should coincide. However, as a semiconductor memory apparatus has been improved with high speed operation, a timing margin between the internal clock signals and the input data signals that is transmitted to respective data input buffers has decreased. Moreover, since timing differences between internal clock signals transmitted to respective data input buffers during high speed operations require detailed attention compared to low speed operations, operational stability in a corresponding data input circuit has become degraded.
To solve this problem, a semiconductor memory apparatus uses a structure in which respective data input buffers are densely arranged adjacent each other. In addition, in order to solve the problem of increased differences in lengths between respective data pads and respective data input buffers, structures are provided in which lengths of respective data input lines are the same with each other.
FIG. 1 is a schematic diagram of a conventional semiconductor memory apparatus. In FIG. 1, a data input circuit 5 of a semiconductor memory apparatus is shown, wherein buffering operations on data input through only five data pads are illustrated for the convenience of description.
In FIG. 1, the data input circuit 5 includes five data pads 1-1 to 1-5, so that respective data pads 1-1 to 1-5 are connected to five data input buffers 3-1 to 3-5 through respective data lines 2-1 to 2-5. The five data input buffers 3-1 to 3-5 respectively buffer input data signals ‘din1’ to ‘din5’ that are input through respective data lines 2-1 to 2-5, to output buffered data signals ‘dbuf1’ to ‘dbuf5’ to an interior of a semiconductor memory apparatus. For this buffering operation, each of the five data input buffers 3-1 to 3-5 receive an internal clock signal ‘clk_int’.
The five data input buffers 3-1 to 3-5 are arranged to neighbor each other. Accordingly, although the internal clock signal ‘clk_int’ is employed as a clock signal having a high frequency, a timing difference of the internal clock signal ‘clk_int’ transmitted to each of the five data input buffers 3-1 to 3-5 is not very large. In addition, all of the five data lines 2-1 to 2-5 located between the five data pads 1-1 to 1-5 and the five data input buffers 3-1 to 3-5 have the same lengths. As shown in FIG. 1, the five data lines 2-1 to 2-5 are arranged to have different configuration pathways, such as data lines 2-2 and 2-3.
Since the five data input buffers 3-1 to 3-5 should be arranged to neighbor each other, they may occupy areas that obstruct a realization of a highly integrated semiconductor memory apparatus. In addition, coupling noises may occur in input data signals ‘din<1:5>’ due to the data lines 2-1 to 2-5 having the different configuration pathways, thereby degrading stability of a data input operation. As a result, a data input circuit of a semiconductor memory apparatus is problematic in occupational area and operational stability, thereby preventing the realization of high speed operation and high integration.